Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. Applications of CAN range from high speed digital communications networks to low cost multiplex wiring. CAN is a high-integrity serial data communications bus for real-time applications. CAN operates at data rates of up to 1 Megabits per second, has excellent error detection and confinement capabilities, and was originally developed for use in automobiles. The interface between the CAN bus and the CPU is usually called the CAN controller. The motivation behind CAN was to make automobiles more reliable, safe and fuel-efficient by improving the interoperability of automotive electronics, engine control units, sensors, anti-skid brake systems, etc., while decreasing wiring harness weight and complexity. Since CAN's inception, the CAN protocol has gained widespread popularity in industrial automation and automotive/truck applications. The robustness of the CAN bus in noisy environments and the ability to detect and recover from fault conditions makes CAN suitable for use with, industrial control equipment, medical equipment, test equipment, mobile and portable machines, appliances, etc.
CAN is an asynchronous serial bus system with one logical bus line. It has an open, linear bus structure with equal bus nodes. A CAN bus consists of two or more nodes. The number of nodes on the bus may be changed dynamically without disturbing the communication of the other nodes.
The CAN logic bus corresponds to a “wired-AND” mechanism, “recessive” bits (mostly, but not necessarily equivalent to the logic level “1”) are overwritten by “dominant” bits (mostly logic level “0”). As long as no bus node is sending a dominant bit, the bus line is in the recessive state, but a dominant bit from any bus node generates the dominant bus state. Therefore, for the CAN bus line, a medium is chosen that is able to transmit the two possible bit states (dominant and recessive). A common physical medium used is a twisted wire pair. The bus lines are then called “CANH” and “CANL,” and may be connected directly to the CAN controller nodes or via a connector thereto.
In the CAN bus protocol it is not bus nodes that are addressed, but rather the address information is contained in the messages that are transmitted. This is done via an identifier (part of each message) which identifies the message content, e.g., engine speed, oil temperature, etc. The identifier additionally indicates the priority of the message. The lower the binary value of the identifier, the higher the priority of the message (more dominant bits).
The original CAN specifications (Versions 1.0, 1.2 and 2.0A) defined the message identifier as having a length of 11 bits, giving a possible 2048 message identifiers. An “extended CAN” specification Version 2.0B allows message identifier lengths of 11 and/or 29 bits to be used (an identifier length of 29 bits allows over 536 Million message identifiers). The CAN specifications (all versions) are incorporated by reference herein for all purposes.
Generally, two approaches may be used for CAN since an architecture for the CAN controller is not covered by the CAN standard, these two approaches are: “BasicCAN” and “FullCAN” (not to be confused with CAN 1 and CAN 2, or standard identifiers and extended identifiers); they differ in the buffering of messages.
The BasicCAN controller architecture is similar to simple UART, except that complete frames are sent instead of characters. Typically, there is a single transmit buffer and a double-buffered receive buffer. For example, a microcontroller puts a frame in the transmit buffer, and receives an interrupt when the frame is sent. When a frame is received in the receive buffer, the microcontroller receives an interrupt to empty the receive buffer and empties the frame from the receive buffer before a subsequent frame is received. In the BasicCAN controller architecture the microcontroller must manage the transmission and reception, and handle the storage of the frames.
The FullCAN controller architecture stores frames in the controller itself. A limited number of frames may be dealt with. Each frame buffer is tagged with the identifier of the frame mapped to the buffer. The microcontroller can update a frame in the buffer and mark it for transmission. Receive buffers can be examined to see if a frame with a matching identifier has been received. In addition, filters may be used to pre-screen a received frame so that only those frames intended for use by the particular CAN controller is stored in a receive buffer.
Standard CAN vs. Extended CAN
The CAN protocol usually comes in two versions: CAN 1.0 and CAN 2.0. CAN 2.0 is backwardly compatible with CAN 1.0, and most new controllers are built according to CAN 2.0. There are two parts to the CAN 2.0 standard: part A and part B. With CAN 1.0 and CAN 2.0A, identifiers must be 11-bits long. With CAN 2.0B identifiers can be 11-bits (a “standard” identifier) or 29-bits (an “extended” identifier). To comply with CAN 2.0 a controller must be either 2.0 part B passive, or 2.0 part B active. If it is passive, then it must ignore extended frames (CAN 1.0 controllers will generate error frames when they see frames with 29-bit identifiers). If it is active then it must allow extended frames to be received and transmitted. There are some compatibility rules for sending and receiving the two types of frames:
CAN 2.0B active controllers will send and accept both standard and extended frames.
CAN 2.0B passive controllers will send and receive standard frames, and will discard extended frames without error.
CAN 1.0 controllers will generate errors when they see extended frames.
So a network where there is a single CAN 1.0 controller on the network cannot live with extended frames on the network; all the controllers must send using standard frames.”
Controller Architectures
The architecture of controllers isn't covered by the CAN standard, so there is a variation in how they are used. There are, though, two general approaches: BasicCAN and FullCAN (not to be confused with CAN 1.0 and 2.0, or standard identifiers and extended identifiers); they differ in the buffering of messages.”
In a BasicCAN controller the architecture is similar to a simple UART, except that complete frames are sent instead of characters: there is (typically) a single transmit buffer, and a double-buffered receive buffer. The CPU puts a frame in the transmit buffer, and takes an interrupt when the frame is sent; the CPU receives a frame in the receive buffer, takes an interrupt and empties the buffer (before a subsequent frame is received). The CPU must manage the transmission and reception, and handle the storage of the frames.”
In a FullCAN controller the frames are stored in the controller. A limited number of frames can be dealt with (typically 16); because there can be many more frames on the network, each buffer is tagged with the identifier of the frame mapped to the buffer. The CPU can update a frame in the buffer and mark it for transmission; buffers can be examined to see if a frame with a matching identifier has been received.”
The intention with the FullCAN design is to provide a set of “shared variables” in the network; the CPU periodically updates the variables (i.e. the contents of frames in the buffer); the CPU also can examine the variables. In practice, things are not so simple (of course) because of concurrency difficulties: while reading a set of bytes from a frame, the controller could overwrite the data with the contents of a new frame, and in many controllers this is signaled only by a status flag.”
In “Basic CAN” implementations, there is generally one double buffered receive channel with one or more associated message acceptance filters. Having but one double buffered message channel means that the processor must be capable of handling the previous message within this time. In “Full CAN” implementations, there are generally up to 15 message buffers or channels, each with one associated message acceptance filter. Having a large number of receive-buffers can be helpful in dealing with bursts of message traffic if the processor is very slow, however, if the total message traffic is such that it overwhelms the processor capability, no amount of buffering can prevent the eventual loss of a message. If a processor's CPU is very slow, to receive many different addressed messages requires separate receive buffers and acceptance filters. With a faster processor, it is possible to use a more limited number of receive buffers with flexibility in the programming of the acceptance filters. In short, the processor must have the bandwidth to service the total traffic on the bus. A plurality of buffers is usually implemented as a compromise. However, each receive buffer has associated a plurality of mask registers and filter registers. This requires a large amount of silicon real estate. Furthermore, each mask and filter can only be used with the respective buffer. If one or more buffers are not in use the respective mask and filter cannot be assigned to a different buffer.
There is, therefore, a need in the art for a CAN implementation that does not require a large number of masks and filter registers and is more flexible than the prior art implementation.